Cypress‘s highly integrated single-chip Bluetooth Low Energy BLE solution to simplify the design of sensor-based low-power IoT applications. The new PSoC 4 BLE programmable system-on-chip offers unprecedented ease of use and high level of integration for custom IoT applications, home automation, medical, sports fitness monitoring and other smart wearable devices. The PRoC·BLE Programmable RF System-on-Chip provides a cost-effective Turnkey solution for Human Interface Devices (HIDs), remote controls and applications requiring specialized wireless connectivity.

Cypress Bluetooth Low Energy BLE solution features a smart Bluetooth radio, a high-performance 32-bit ARM with ultra-low power mode? The Cortex-M0 core, programmable analog blocks, and Cypress‘s industry-leading CapSense capacitive touch-sensing capabilities complete the system. Together, these technologies provide unmatched system value, longer battery life, customizable sensing capabilities, and a beautiful and intuitive user interface for Bluetooth Smart products.

Cypress PSOC/PROC BLE products are designed and developed through the PSoC Creator graphical programming IDE. Cypress simplifies the Bluetooth low energy protocol stack and configuration files into a new license-free, GUI-based Bluetooth BLE component, which is integrated in PSoC Creator. In the environment (IDE), the component can be dragged and dropped into the design project to realize the graphical configuration. Of course Eclipse? Users of PSoC Creator and other ARM-based tools can also use PSoC Creator to custom design their Bluetooth low energy solutions and export the design to their preferred IDE.

Cypress President and CEO T.J. Rodgers said: "Cypress‘s new Bluetooth low energy solutions have a solid foundation: our powerful ARM-based programmable controllers have shipped more than 100 million units, and we also have low power Expertise in wireless connectivity technology, as well as our market-leading capacitive touch sensing technology. Cypress‘s BLE solutions offer unprecedented levels of integration and ease of design for immediate use in IoT, wearable electronics, and other Bluetooth smart applications. fast-growing market."

The PSoC 4 BLE family adds a Bluetooth Smart radio to the highly flexible PSoC 4 architecture, with an integrated programmable analog front end for sensor interface and programmable digital peripherals for digital logic and control functions. This combination greatly simplifies the design of IoT applications, making it a compelling custom single-chip solution. To further accelerate time-to-market, PSoC 4 BLE and PRoC BLE also offer an on-chip Balun that simplifies antenna design while reducing board size and system cost.

The Cypress low-energy Bluetooth solution also includes a programmable CapSense touch-sensing module, whose built-in CypressSmartSense auto-tuning algorithm recognizes two-finger gestures and eliminates the need for manual tuning at all. Cypress is a leader in touch sensing, having shipped more than 1 billion CapSense touch sensing controllers to date, replacing more than 5 billion in mobile phones, laptops, consumer electronics, white goods, automotive and other systems Mechanical keys.

Features of Cypress‘s Single-Chip Bluetooth Low Energy BLE Solution:

1. 32-bit MCU subsystem

48 MHz ARM Cortex-M0 CPU with single-cycle multiply

Flash memory up to 128 KB with read accelerator

SRAM capacity up to 16 KB

2. BLE wireless and subsystem

2.4 GHz RF receiver capable of driving 50 antennas

digital PHY

Link layer engine supports master mode and slave mode

RF output power range: –18 dBm to +3 dBm

RX Sensitivity: –92 dBm

RX current: 18.7 mA

TX current is 16.5 mA at 0 dBm

RSSI: 1 dB resolution

3. Programmable analog module

The four op amps include reconfigurable high-drive external/high-bandwidth internal drivers, comparator mode, and ADC input buffer functionality. Ability to operate in deep sleep mode.

The 12-bit resolution, 1 Msps sample rate SAR ADC includes differential mode, single-ended mode, and a channel sequencer with signal averaging.

Two current DACs (IDACs) on each pin for general purpose or capacitive sensing applications

Programmable digital block with two low-power comparators operating in deep-sleep mode

Four programmable logic blocks (aka Universal Digital Blocks UDBs), each containing 8 macrocells and data paths

Cypress provides a library of peripheral components, user-defined state machines, and Verilog inputs

4. Timing and Pulse Width Modulation

Four 16-bit Timer/Counter Pulse Width Modulator (TCPWM) modules

Center Aligned Mode, Edge Mode and Pseudo Random Mode

Comparator-based kill signal for motor drives and other high-reliability digital logic applications Up to 36 programmable GPIOs

56-Pin 7 mm × 7 mm QFN Package

3.51 mm × 3.91 mm 68-pin ball pad CSP package

Any GPIO pin can be used as CapSense, LCD, analog or digital