STMicroelectronics (ST) uses ARM‘s Cortex-M7 core STM32 F7 new series of microcontrollers (MCU).

ST‘s STM32 F7 series significantly outperforms the previous high-performance 32-bit Cortex-M microcontroller STM32 F4, doubling processing and DSP performance through a seamless upgrade path.

 

STMicroelectronics STM32 F7 is the most intelligent and smartest product line in the STM32 family. Thanks to the highest performance of the Cortex-M7, the STM32F7 presents the highest performance, but the energy efficiency ratio of the F7 remains as good as ST‘s previous products. In order to give full play to the powerful algorithms and capabilities of the STM32F7 core, more peripherals and innovative architectures are equipped outside the core. This product design is based on the existing mature process platform, and the product is brought to market at the fastest speed. From the past to today, ST and ARM have been investing together in the development and development of the ecosystem, and the latest STM32 F7 product line also benefits from the existing complete ecosystem.

According to Daniel Colonna, Marketing Director of STMicroelectronics Microcontrollers, ST is a very close partner of ARM. When designing the Corex-M7, ST was an important partner who participated in the design and development of this core. The first evaluation versions are based on STM32 F7 products in 216-pin package.

The reason why STM32 F7 is the smartest and smartest product STM32 is not only because it has a Cortex-M7 core, but also this core is equipped with more intelligent peripherals and buses. In order to further give full play to the high performance of the STM32 F7 core, ST has fully designed and processed the system architecture in three aspects: the first one has a flash memory accelerator. Second, the CPU supports the first-level cache, and these two parts can realize zero-wait for executing programs. Third, the 64-bit AXI bus matrix architecture is used in the matrix, and the specially designed DMA can realize zero wait for data storage and instruction delivery. Finally, ST has made more improvements and enhancements in terms of Memory, and designed a flexible SRAM allocation architecture to meet different applications. To give full play to the performance of Cortex-M7, we designed this architecture, and we can see that a variety of DMAs allow data and instructions to be transferred between CPU and memory with zero wait. In this way, 7 buses are transmitted at the same time.

In addition, if it is an urgent program to be executed, such as some urgent task processing of motor control, we also have an ITCM RAM, which can execute tasks with high priority. The data and programs stored in the external memory are pre-cached through the first-level cache. Thus, the maximum intelligence of the CPU brain can be exerted without waiting.

So from a chip perspective, the core is a very important part, but not the whole. In order to give full play to the powerful performance of the kernel, we hope that the entire system architecture can meet and cooperate with the performance of the CPU. So seeing ST‘s entire chip design, the final performance is consistent with the core. Therefore, ARM mentioned that the performance of ARM Cortex-M7 can reach 1000 CoreMark, which can also be seen in STM32 F7.