As chip graphics become smaller and smaller, low-power chip design, as an emerging chip design method, will play an increasingly important role in the chip field now and in the future. Low-power chip design promotes smartphone , the rapid development of industries such as mobile devices, the Internet of Things, and high-performance computing.

Chip power consumption is mainly composed of three parts: dynamic power consumption (also called switching power consumption, which is caused by the logic gate charging and discharging the load capacitor during operation), and short-circuit power consumption (which is caused by transient short circuit during the switching of the logic circuit) , and static power consumption (also called leakage power consumption is caused by leakage current in logic circuits), therefore, low-power design is mainly carried out around how to reduce the power consumption of these three parts.

The following ShenZhen Hao Qi Core Technology  will introduce several typical power IC low-power design and management methods:

​​

1. Low dropout regulator: It is a DC linear regulator that uses feedback for voltage regulation. Its circuit consists of a PMOS transmission gate, a high-gain error amplifier, and a voltage divider resistor (sometimes with a decoupling capacitor) . It can provide a wide range of power supply voltage output, and has the advantages of low noise, low cost, and high integration, so it is widely used in low-power designs.

2. Dynamic voltage-frequency adjustment: It is aimed at reducing dynamic power consumption. Dynamic power consumption is proportional to the operating frequency of the circuit, and also proportional to the square of the supply voltage. Therefore, if the working state of the circuit can be judged at any time, and the working frequency and power supply can be adjusted accordingly, the purpose of reducing power consumption can be achieved. The dynamic voltage-frequency adjustment controller will determine the power supply voltage and working frequency according to the working state of the circuit.​​

The purpose of dynamic voltage-frequency adjustment is to reduce the power consumption when the chip is working, so the designer needs to know the working status of each module on the chip very well in order to design a good dynamic voltage-frequency adjustment controller. At the same time, the voltage should also be considered in timing optimization. The change. A good dynamic voltage-frequency adjustment can save 20% of dynamic power consumption.

3. Power valve: It is aimed at static power consumption (power consumption caused by leakage current). When some functional modules are not working, the power supply is disconnected. In the sub-threshold range of the transistor, the leakage current is proportional to the voltage. Exponential relationship, so this method has a very significant effect on reducing static power consumption.

To realize an ideal power valve, there are many requirements for this small switch: the resistance value should be small when it is turned on; the resistance value should be large when it is turned off (to reduce its leakage current); Respond quickly. In fact, the power valve in the chip is not just a single transistor switch, but consists of hundreds of transistor switches. How to place these hundreds of power valves requires accurate calculation and analysis, and they are opened in a certain order and time. In this way, the inrush current can be effectively controlled.

Power consumption will affect a series of issues such as circuit performance, chip heat dissipation, and chip reliability, and has become the most important factor in current chip design. The above-mentioned low-power design and optimization at the circuit level hope to help you. Help, with the continuous improvement of device technology, circuit design, system integration, and software development, low-power design will continue to develop in all aspects of the above.