One，Problems

In many areas of the electronics industry, the incorporation of flip-chips into new products shows a growing pattern. Therefore, numerous design, material, process and equipment related variables must be understood to ensure the successful implementation and survival of this technology. For example, the handling and placement of bare chips creates new challenges not normally encountered in standard surface mount assembly. A customer recently asked, "We‘re seeing an increase in the number of skewed chips in our flip-chip assembly process - what could be causing this and how can we correct it?"

Second, the cause of the problem

Die skew is a process issue that can occasionally occur when dealing with bare die. Several factors in the flip-chip assembly process can cause such placement defects, including improper equipment settings, incorrect process parameters, and incompatible assembly materials. In addition, placement accuracy is not only affected by the die attach process, but also by other manufacturing processes, such as fluxing, board transfer, and solder reflow. It is often a challenge for manufacturing engineers to rapidly determine and eliminate the variables responsible for this particular skew problem.

For the aforementioned special case of chip skew, we follow a series of method steps to find the cause of the problem and provide a solution. In working with the customer, the initial focus was on determining which process step caused the problem. Process checks are performed on upstream and downstream processes, primarily fluxing and solder reflow, to determine the potential impact of each process. After concluding that the process and equipment conditions are within specification and ensuring that all independent and dependent variables are correct, we observe the die attach at the customer‘s factory. Observations show that different nozzle types produce significant skewing effects on various chip batches.

The placement process was then simulated on a surface mount line with the same variables and conditions as those used at the customer‘s factory. Using the customer‘s actual product and various chip lot numbers, during the placement process, high-speed photography is performed when two nozzle models are used. The video shows that the chip also adheres to the B-type nozzle (rubber) while the chip is released, but no chip adhesion when the A-type nozzle is used. The placement was done without flux to highlight the adhesion of the chip to the nozzle. Rigid support for the board to reduce the elastic effect of the board. Information was also collected to determine the interaction of each nozzle type with various chip lot numbers.

Contamination on the chip and nozzle, as well as the surface finish of the chip and nozzle, were thoroughly investigated. Samples were characterized, including solvent extraction, scanning electron microscopy (SEM), and Fourier transform infrared spectroscopy (FTIR), for both nozzle type (old and new) and individual chip lot numbers. Analysis revealed that backside recesses were present on failed chip lots (approximately 30mm diameter, 8mm depth). Organic compounds are also found - mainly the cling and free oxyhydroxide family. This situation can lead to die attach problems, either due to excessive adhesion, or due to the localized effects of vacuum. In addition, FTIR analysis revealed a family of compounds on the old nozzles (both Type A and Type B), indicating a free oxyhydroxide family, which may be found in organic acids, alcohols, and solvents. The possible cause of chip sticking is excessive adhesion between the chip and the nozzle due to the interaction or reaction of the hydroxide family. A new nozzle was installed on the placement machine and the skew problem was corrected immediately.

In this particular case, the solution to the chip skew problem was a simple correction. The condition of the nozzle surface is critical to obtain proper adhesion and separation between the nozzle and the chip. Proper nozzle surface cleaning methods are critical to ensuring nozzle (and placement) performance.