Features
SHARC+ Core infrastructure
800MHz (max) or 1GHz (max) Core clock frequency
640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance
32-bit, 40-bit & 64-bit floating point support
32-bit fixed point
Byte, short-word, word, long-word addressed
Memory
1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases
Advanced Hardware Accelerators
Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power
Security Crypto Engines with OTP
Powerful DMA System
Innovative Digital Audio Interface (DAI) includes:
8x Full SPORT interfaces w/TDM & I2S modes
2x S/PDIF Rx/Tx, 8 ASRC pairs
4x Precision Clock Generators
24 Buffers
Other Peripheral Connectivity / Interfaces:
2x Quad SPI, 1x Octal SPI
MLB 3-pin
4x I2C, 2x UARTs
6x General Purpose Timer, 1x General Purpose Counter
2x Watchdog Timers
2-ch 12bit Housekeeping ADCs
22 GPIO pins, 24 DAI pins
Thermal Sensor
Package
14mm x 14mm 120-lead LQFP_E
Additional Features
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1 GHz
AEC-Q100 qualified for automotive applications