SPC5642AF2MLU1
Feature
1、150 MHz e200z4 Power Architecture core：
Variable length instruction encoding (VLE)
Superscalar architecture with 2 execution units
Up to 2 integer or floating point instructions per cycle
Up to 4 multiply and accumulate operations per cycle
2、Memory organization：
2 MB on-chip flash memory with ECC and read-while-write (RWW)
128 KB on-chip SRAM with standby functionality (32 KB) and ECC
8 KB instruction cache (with line locking), configurable as 2- or 4-way
14 + 3 KB eTPU code and data RAM
4 crossbar switch (XBAR)
24-entry MMU
3、Fail Safe Protection：
16-entry Memory Protection Unit (MPU)
CRC unit with 3 submodules
Junction temperature sensor
4、Interrupt：
Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)
64-channel eDMA
5、Serial channels：
3 eSCI modules
3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])
3 FlexCAN modules with 64 message buffers each
1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
6、 Flexible supply scheme：
5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V
Description
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This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications.
It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M devices.
The microcontroller’s e200z4 host processor core is built on the Power Architecture® technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration System.
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