In this article, I will analyze the DCI technology of Xilinx series FPGAs, hoping to help you reference.

One、An overview of the DCI technology of Xilinx series FPGAs:

As the FPGA chip is larger and the system clock is higher, the PCB board design and structural design become more difficult. With the increase of the speed, the signal integrity between boards becomes very critical. If there are key signals on the PCB board, it is necessary to Impedance matching is performed to avoid signal reflection and oscillation. Xilinx provides DCI that can perform impedance matching inside the chip, and the matching resistor is more connected to the chip, which can reduce the number of components, save the area of ​​the PDB board, and make wiring more convenient.

The traditional impedance matching is to terminate a resistor on the PCB board. Ideally, the output impedance of the source end is considered to be very small, while the input impedance of the receiving end is considered to be very large. In actual circuits, it can be ignored. Only the traces on the PCB are considered, and the characteristic impedance of the PCB is seen from the receiving end. Should be equal to the source termination resistance so that current flows from the source to the sink without causing reflections.

Second, the impedance matching principle of Xilinx series FPGA:

Impedance matching refers to a working state in which the load impedance and the internal impedance of the excitation source are matched to each other to obtain the maximum power output. For circuits with different characteristics, the matching conditions are different. In a pure resistance circuit, when the load resistance is equal to the internal resistance of the excitation source, the output power is the largest, and this working state is called matching, otherwise it is called mismatching. When the internal impedance of the excitation source and the load impedance contain reactance components, in order to obtain the maximum power for the load, the load impedance and the internal resistance must satisfy the conjugation relationship, that is, the resistance components are equal, and the reactance components are only equal in value and opposite in sign. Such matching conditions are called conjugate matching.

In high-speed design, impedance matching is related to the quality of the signal. Impedance matching technology can be said to be rich and varied, but how to apply it reasonably in a specific system needs to measure many factors. For example, in the design of our system, many of them are series matching of source segments. For what circumstances need to be matched, what method of matching is used, and why this method is used. For example, most of the differential matching adopts parallel terminal matching; the clock adopts series source matching.

Three、DCI technology of Xilinx series FPGA:

According to the level standard of I/O, DCI technology can control the output impedance of the driver, and can also add parallel termination on the driver or receiver. The purpose is to precisely match the characteristic impedance of the transmission line. DCI technology calculates the impedance inside the I/O based on high precision reference resistors on VRP and VRN. And it can continuously compensate for impedance changes caused by temperature and voltage changes.

For impedance-controlled drivers, the DCI matches the impedance to two external reference resistors, or half of the two reference resistors.

For parallel termination, including transmitter and receiver, DCI technology brings the termination resistor closer to the output driver or input buffer. For 7 series FPGAs, DCI technology is only used in HP I/O banks, not HR I/O banks. Xilinx DCI uses two multiplexed pins to adjust driver impedance or parallel termination resistors. These two pins are VRN and VRP respectively. VRN must be pulled up to VCCO through a reference resistor Rref, while VRP must be pulled down to ground through a reference resistor Rref. The resistance of this Rref is generally equal to the characteristic impedance of the PCB trace or twice the impedance. To use DCI technology in a design, the following conditions need to be met:

(1) The signal pin is in the HP I/O BANK, and the standard of the pin is declared with DCI in the constraint;

(2) Connect a high-precision reference resistor to VRN and pull it up to Vcco;

(3) Connect a high-precision reference resistor to the VRP and pull it down to the ground;

(4) Both VRN and VRP are in the same HP bank. Unless DCI iteration is used, DCI iteration only needs the HP master bank.

(5) The DCI calculation can be reset through the DCIRESET primitive. By sending RST high pulse to DCIRESET, DCI starts to calculate the impedance value and all I/Os that use DCI do not work at this time until the LOCKED signal is pulled high.

1. Impedance control driver

For impedance controlled drivers, DCI offers two types of impedance matching:

(1) equal to the reference resistance

(2) equal to half of the reference resistance

In this case, R must be equal to 2Z0, and the level standard should be DCI_DV2, such as the primitives of LVDCI_DV2_15 and LVDCI_DV2_18. This method is mainly used to reduce static power consumption.

2. Parallel terminals (discrete resistors)

For parallel termination, DCI uses a Thevenin equivalent circuit or discrete resistors, using the level of Vcco/2.

Fourth, the tri-state DCI of Xilinx series FPGA:

For some level standards, such as SSTL and HSTL, the primary standard only supports unidirectional signals, while the secondary standard supports both unidirectional and bidirectional signals. When discrete terminals are used, DCI only controls the impedance of the discrete terminals instead of the driver. impedance, so for bidirectional signals, when it is used as a driver, the application of discrete termination needs to be turned off. XILINX provides a DCI-T standard to meet this requirement, just change the corresponding level standard to this one with DCI-T. Tri-state DCI is only suitable for bidirectional signals.

Five, the DCI iteration of Xilinx series FPGA:

7 series FPGAs can use DCI iteration. DCI iteration means that the I/O banks in the same column can share a pair of reference resistors, that is, as long as the RFN and RFP of the master bank in the I/O banks in this column are connected to the corresponding resistors, The RFN and RFP of other slave banks do not need to be connected to the reference resistor. This greatly reduces the number of components and also reduces power consumption.

DCI iteration needs to follow the following rules:

(1) The pins that require DCI iteration must be on the same column of BANK;

(2) The same column BANK needs to be divided into MASTER and SLAVE BANK, they should have the same Vcco and Vref;

(3) BANKs that are on the same column of BANKs but do not use DCI technology may not follow the second rule;

(4) In order to implement this DCI iteration, the DCI_CASCADE Constraint needs to be used.

Constraint grammar rules:

CONFIG DCI_CASCADE = "...";

E.g:

CONFIG DCI_CASCADE = "11 13 15 17";

In short, for 7 series FPGAs to use DCI technology correctly, do the following:

(1) Vcco must be based on a suitable level standard;

(2) Use the correct DCI I/O BUFFER through the level standard attribute or in the code instantiated in HDL;

(3) The DCI technology requires that the VRN and VRP pins in the corresponding bank are used to connect the correct reference resistors. For the DCI iteration technology, only the VRN and VRP pins in the master bank are used to connect the correct reference resistors. There is a situation that when DCI (with impedance control driver) is only used as input, and these pins are the only pins that use DCI level, then the BANK does not need to connect VRN and VRP to the reference resistor.

Six, Xilinx series FPGA precautions:

LVDS and LVDS25 cannot use DCI technology for termination, it can only be matched through internal termination resistors.

Seven、Summary of Xilinx series FPGAs:

The main function of DCI technology is to ensure the integrity of the signal, prevent the reflection of the signal, and achieve the matching function.